This hardware component is divided into multiple banks in a speed-up technique known as interleaving. This component typically operates by having a (10[1])capacitor charged and discharged by a sense amplifier. The delay stemming from this component's strobe signal is known as CAS latency. This component implements level three of a hierarchy that begins with the registers (10[1])at level one. Single row addresses are sent for multiple locations in this component's fast paging mode. Increased bandwidth came with the fifth version (-5[1])of a form of this component (10[1])that transfers data twice per clock cycle, or double (-5[1])data (10[1])rate. This computer component is typically sold in multiples of two gigabytes, with (10[1])typical desktops containing eight or sixteen gigabytes. For 10 (10[1])points, (10[1])name this type of ■END■