To make certain uncommon events “precise,” these devices sequentially retire the contents of an ROB (“R-O-B”). One unsuccessful design invented for these devices co-located their inputs in “very long words” to extract ILP. These devices employ dynamic scheduling and eliminate anti-dependencies by using reservation stations in Tomasulo's algorithm. Write-back is the last of five concurrently executing pipeline stages in early devices of this kind from the RISC (“risk”) family. The simplest of these devices process their inputs in a loop consisting of fetch, decode, and execute stages. These devices expose an interface called the instruction set architecture, whose examples include MIPS (“mips”) and x86 (“X-eighty-six”). For 10 points, what devices run general purpose machine code and are designed by Arm and Intel? ■END■
ANSWER: CPUs [or central processing units; accept CPU cores; accept (computer) microprocessors; prompt on cores by asking “cores of what devices?”; prompt on SoCs or systems on a chip or system-on-chips by asking “what components of an SoC?”; prompt on computers; reject “(integrated) circuits” or “ICs”; reject “chips”] (Reorder buffers are used to implement precise exceptions. VLIW and Tomasulo’s algorithm aim to maximize instruction-level parallelism.)
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= Average correct buzz position